1. Field of the Invention
The present invention relates to taking-in or introduction of data with great jitter due to interference between codes, and more particularly to taking-in of sync or phase-locked data for improving permissible phase shift, jitter or margin in a reproduction signal in a data read-out circuit of an optical magnetic disk, an optical disk and a magnetic disk drive.
2. Description of the Related Art
Now referring to FIGS. 1, 2 and 3, an explanation will be given of the conventional sync or phase-locked data introduction system and circuit.
FIG. 1 shows an arrangement of the conventional sync data taking-in or introduction system. As seen from FIG. 1, this system is composed of a phase-locked loop (PLL) 4 and a latch 14. In operation, a read code signal 5 which is read, detected in its peak and pulsated is introduced in PLL 4 which generates a sync or phase-lock clock in synchronism or phase-locked with the read code 5. The latch 14 takes in the read code 5 as a sync data with the sync clock generated by PLL 4 and transfers it a read data 6 as well as a read clock 7 to a succeeding stage.
FIG. 2 shows the principle of a window, i.e., a period which can be used for data introduction during one period of a VCO (voltage controlled oscillator). In FIG. 2, VCO-P 8 and VCO-N 9 denote two-phase phase-inverted sync clocks generated by PLL 4 or VCO outputs. As seen from FIG. 2, a conventional window 15, which is conceptually taken as a discrimination window for deciding whether each bit of the read code 5 is "1" or "0", ranges from the rising edge of VCO-P 8 to a succeeding rising edge, and the rising edge of VCO-N 9 is centered within the window. Ideally, this window has a width corresponding to one period of VCO-P 8 (or VCO-N 9). If the rising edge of the read code is detected within the range of one period, the data at the corresponding bit is decided to be "1". However, an actual window 16, as described later, involves window loss 17 containing several kinds of elements. This window has a relatively short width with the window loss subtracted from one period length (i.e., one bit length of the read code 5) of VCO-P 8 (or VCO-N 9). Thus, only if the rising edge is detected within the window, the data "1" is correctly recognized. As a result, the window loss may lead to an erroneous operation.
With reference to FIGS. 3A and 3B, a concrete explanation will be given of the operation of an exemplary conventional latch circuit. As seen from FIG. 3A, the conventional latch circuit is composed of two D-type flip-flops FF 141 and FF 142, and a two-input NAND 143. A read gate 18 fixed at high "H" is taken in FF 141 at the rising edge of the read code 5. Then, it is assumed that the rising edge of the read code 5 is synchronous with that of VCO-P 8 generated by PLL 4. An output 144 from FF 141 is taken in FF 142 at the rising edge of VCO-N 9 to be outputted as a read data 6. A CL input of FF 142 is also set at "H". Then, the NAND output of the output 144 from FF 141 and the read data 6 resets FF 141 so that the rising edge of the read code 5 is waited again.
A typical latch circuit similar to the above conventional latch circuit is disclosed in e.g., an article, V. Condito et al "A 18 MB/S BICMOS DISK DRIVE DATA SEPARATOR" in Proceedings 15.2.1-15.2.4 of IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE held in 1990.
The above prior art has the following defects. The width of the window 16 becomes theoretically smaller than one period of VCO-P 8 (or VCO-N 9) due to window loss. Specifically, the ideal window 15 is narrowed by the window loss 17 including a difference in delay of a read code signal in the latch 14 and VCO, an ordinary phase difference between the data and clock in PLL 4, a phase shift between the edges of VCO-P 8 and VCO-N 9 and a jitter component of the read code 5. This provides an actual window 16 with a narrowed width. Thus, the window loss may lead to some lack or error in the data.
In particular, in high speed data transfer required in recent years, the width of one period of VCO-P 8 or VCO-N 9 has become short so that the accuracy of transfer will be relatively greatly influenced by the window loss; this is an obstacle to high speed data transfer.